Semiconductor over insulator (SOI) devices provide numerous benefits in contemporary integrated circuit technology. An SOI device includes a semiconductor mesa overlying a buried insulating layer, which itself overlies a semiconductor substrate. Typically, a transistor is formed within the semiconductor mesa. During oxide deglaze cycles, which are a normal part of integrated circuit processing of mesa isolated SOI transistors, it is difficult to avoid etching of the exposed buried insulating layer. The etching of the exposed buried layer causes unwanted oxide undercutting of the SOI mesa. This undercutting has been shown to cause numerous problems with the devices ultimately constructed within the mesa. For example, the undercutting region has been shown to degrade gate oxide integrity at the bottom corner of the semiconductor mesa. Additionally, the undercutting causes a decrease in the radiation hardness of the device.
The prior art methodologies for forming a semiconductor mesa in a SOI architecture result in the above-mentioned undercut regions. Accordingly, the undesirable results of degradation of gate oxide integrity and increased susceptibility to the effects of radiation currently exist in contemporary SOI mesa devices. Therefore, a need has risen for an SOI mesa architecture and methodology which significantly reduces or eliminates the effects of undercutting discussed above.